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?300 ma, ultralow noise, high psrr, low dropout linear regulator data sheet adp7183 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features input voltage range: ?2.0 v to ?5.5 v maximum output current: ?300 ma fixed output voltage options: ?0.5 v to ?4.5 v adjustable output from ?0.5 v to ?v in + 0.5 v low output noise: 4 v rms from 100 hz to 100 khz noise spectral density: 20 nv/hz, 10 khz to 1 mhz power supply rejection ratio (psrr) at ?300 ma load 75 db typical at 10 khz 62 db typical at 100 khz 40 db typical at 1 mhz low dropout voltage: ?130 mv typical at i out = ?300 ma initial output voltage accuracy (v out ): 0.5% at i out = ?10 ma output voltage accuracy over line, load, and temperature: 2.6% operating supply current (i gnd ): ?0.6 ma typical at no load low shutdown current: ?2 a typical at v in = ?5.5 v stable with small 4.7 f ceramic input and output capacitor positive or negative enable logic current-limit and thermal overload protection 8-lead, 2 mm 2 mm lfcsp package supported by adisimpower voltage regulator design tool applications regulation to noise sensitive applications: analog-to-digital converters (adcs), digital-to-analog converters (dacs), precision amplifiers communications and infrastructure medical and healthcare industrial and instrumentation typical application circuits v out = ?3.3 v c out 4.7f c a 1f c afb 10nf +1.25v 0v ?1.3v off on vin en vreg gnd vout sense va vafb c in 4.7f v in = ?3.8v c reg 1f adp7183 ep 12897-001 figure 1. adp7183 with fixed output voltage, v out = ?3.3 v v out = ?2.5 v c out 4.7f +1.25v 0v ?1.3v off on vin en vreg gnd vout sense va vafb c in 4.7f v in = ?3v c reg 1f adp7183 c a 1f c afb 10nf r2 24.9k ? r1 100k ? ep 12897-002 figure 2. adp7183 with adjustable output voltage, v out = ?2.5 v general description the adp7183 is a complementary metal oxide semiconductor (cmos), low dropout (ldo) linear regulator that operates from ?2.0 v to ?5.5 v and provides up to ?300 ma of output current. this ldo regulator is ideal for regulation of high performance analog and mixed-signal circuits operating from ?0.5 v down to ?4.5 v. using an advanced proprietary architecture, the adp7183 provides high psrr and low noise, and it achieves excellent line and load transient response with a small 4.7 f ceramic output capacitor. the adp7183 is available in 15 fixed output voltage options. the following voltages are available from stock: ?0.5 v, ?1.0 v, ?1.2 v, ?1.5 v, ?1.8 v, ?2.0 v, ?2.5 v, ?3.0 v, and ?3.3 v. additional voltages available by special order are ?0.8 v, ?0.9 v, ?1.3 v, ?2.8 v, ?4.2 v, and ?4.5 v. an adjustable version is also available that allows output voltages that range from ?0.5 v to ?v in + 0.5 v with an external feedback divider. the enable logic feature is capable of interfacing with positive or negative logic levels for maximum flexibility. the adp7183 regulator output noise is 4 v rms independent of the output voltage. the adp7183 is available in an 8-lead, 2 mm 2 mm lfcsp, making it not only a very compact solution but also providing excellent thermal performance for applications requiring up to ?300 ma of output current in a small, low profile footprint.
adp7183 data sheet rev. 0 | page 2 of 19 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and outp ut capacitor recommended specifications ... 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd cautio n .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 13 adjustab le mode operation ..................................................... 13 enable pin operation ................................................................ 13 start - up time ............................................................................. 14 applications information .............................................................. 15 adis impower design tool ....................................................... 15 capacitor selection .................................................................... 15 undervoltage lockout (uvlo) ............................................... 16 current - limit and thermal overload protection ................. 16 thermal considerations ............................................................ 17 pcb layout considerations ...................................................... 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision hi story 10/2016 revision 0 : initial version
data sheet adp7183 rev. 0 | page 3 of 19 specifications v in = (v out ? 0.5 v) or ? 2 v (whichever is greater), en = v in , i out = ? 10 ma, c in = c out = 4.7 f, c afb = 10 nf, c a = c reg = 1 f , t a = 25 c for typical specifications, t j = ? 40 c to +125 c for minimum/maximum specifications, unless otherwise noted. table 1. parameter symbol test conditions /comments min typ max unit input voltage range v in ? 2.0 ? 5.5 v operating supply current i gnd i out = 0 a ? 0.6 ? 0.90 ma i out = ? 300 ma ? 4.0 ? 7.0 ma shutdown current i gnd - sd en = gnd, v in = ? 5.5 v ? 2 ? 7 a output noise 1 out noise 10 hz to 100 khz, c afb = 1 nf 7 v rms 10 hz to 100 khz , c afb = 10 nf 5 v rms 100 hz to 100 khz , c afb = 1 nf 6 v rms 100 hz to 100 khz, c afb = 10 nf 4 v rms noise spectral density 1 out nsd 100 hz , c afb = 1 nf 300 nv/hz 100 hz, c afb = 10 nf 100 nv/hz 10 khz to 1 mhz, c afb = 1 nf to 1 f 20 nv/hz power supply rejection ratio 1 psrr i out = ? 300 ma , v out = ?3.3 v, v in = ?3.8 v at 1 khz 85 db at 10 khz 75 db at 100 khz 62 db at 1 mhz 40 db output voltage v out ? 0.5 ?4.5 v output voltage accuracy i out = ?10 ma ? 0.5 +0.5 % ?1 ma < i out < ?300 ma , v in = (v out ? 0.5 v) to ?5.5 v ? 2.6 +2.6 % output voltage reference f eedback v afb adjustable model voltage refere nce ? 0.487 ? 0.5 ? 0.513 v v afb accuracy adjustable model , v in = ? 2 v, i out = ? 10 ma ? 2.6 +2.6 % regulation line v out /?v in v in = (v out ? 0.5 v) to ?5.5 v ?0.1 +0.3 %/v load 2 ?v out /?i out i out = ?1 ma to ?300 ma 0.8 2.6 %/a input bias current sense sense i- bias ?1 ma < i out < ?300 ma, v in = (v out ? 0.5 v) to ?5.5 v ?10 na v afb v afb - bias ?1 ma < i out < ?300 ma, v in = (v out ? 0.5 v) to ?5.5 v ?10 na dropout voltage 3 v dropout i out = ?100 ma ?40 ?65 mv i out = ?300 ma ?130 ?220 mv pull - down resistance v en = 0 v output voltage v out - pull v out = ?1 v 280 regulated input supply voltage v reg - pull v reg = ?1 v 1.3 k low noise reference voltage v a - pull v a = ?1 v 50 start - up time 4 t start - up v out = ?4.5 v, c afb = 1 nf, c a = 1 f 15 ms v out = ?4.5 v, c afb = 10 nf, c a = 1 f 55 ms v out = ?1.2 v, c afb = 1 nf, c a = 1 f 4 ms v out = ?1.2 v, c afb = 10 nf, c a = 1 f 10 ms v out = ?0.5 v, no c afb , c a = 1 f 1.5 ms current - limit threshold 5 i limit ?400 ?600 ?800 ma thermal shutdown threshold ts sd t j rising 150 c hysteresis ts sd - hys 15 c
adp7183 data sheet rev. 0 | page 4 of 19 parameter symbol test conditions /comments min typ max unit undervoltage lockout thresholds input voltage rising uvlo rise ?1.77 v falling uvlo fall ?1.58 v hysteresis uvlo hys 90 mv en input (negative) ?2 v v in ?5.5 v logic high v en - neg - high v out = off to on ?1.3 ?1.16 v logic low v en - neg_low v out = on to off ?0.96 ?0.88 v hysteresis en hys - neg 191 mv leakage current i en - lkg en = v in or gnd ?0.25 a en input (positive) ?2 v v in ?5.5 v logic high v en - pos - high v out = off to on 0.96 1.25 v logic low v en - pos - low v out = on to off 0.5 0.89 v leakage current i en - lkg v en = 5 v, v in = ?5.5 v 4.0 6.0 a 1 guaranteed by characterization but not production tested. 2 based on an endpoint calculation using ?1 m a and ?300 ma loads. 3 dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. dropout applies only for output voltages below ?2 v. 4 start - up time is defined as the time between the rising edge of en to vout being at 90 % of its nominal value. 5 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current - limit threshold for a ? 3 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of ? 3.0 v, or ? 2.7 v. input and output cap acitor recommended s pecifications table 2. parameter symbol test conditions /comments min typ max unit capacitance t a = ?40c to +125c minimum c in and c out capacitance 1 c in , c out 3.3 4.7 f minimum c a and c reg capacitance 2 c a , c reg 0.7 1 f minimum c afb capacitance 3 c afb 0.7 10 nf capacitor equivalent series resistance ( esr ) r esr 0.1 1 the minimum input and output capacitance must be greater than 3.3 f over the full range of operating conditions. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with any ldo. 2 the minimum c a and c reg capacitance must be greater than 0.7 f over the ful l range of operating conditions. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with any ldo. 3 the minimum c afb capacitance must be greater than 0.7 nf over the full range of operating conditions. x7r and x 5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with any ldo.
data sheet adp7183 rev. 0 | page 5 of 19 absolute maximum ratings table 3. parameter rating vin to gnd +0.3 v to ?6 v vout to gnd +0.3 v to ?v in en to gnd +5.0 v to ?6 v va to gnd +0.3 v to ?6 v vafb to gnd +0.3 v to ?6 v vreg to gnd +0.3 v to ?2.16 v sense to gnd +0.3 v to ?6 v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp7183 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low printed circuit board (pcb) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction to ambient thermal resistance of the package ( ja ). use the following equation to calculate the junction temperature (t j ) from the ambient temperature (t a ) and power dissipation (p d ): t j = t a + ( p d ja ) the junction to ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction to ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the ja value may vary, depending on the pcb material, layout, and environmental conditions. the specified ja values are based on a 4-layer, 4 in. 3 in. circuit board. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. table 4. thermal resistance package type ja jc unit cp-8-27 1 68.8 10.0 c/w 1 thermal impedance simulated values ar e based on jedec 2s2p thermal test board with four thermal vias. see jedec jesd51. esd caution
adp7183 data sheet rev. 0 | page 6 of 19 pin configuration and fu nction descriptions 3 va 4 vafb 1 vout 2 sense 6gnd 5en 8vin 7vreg adp7183 top view (not to scale) notes 1. exposed pad. the exposed pad enhances the thermal performance and is electrically connected to vin inside the package. it is recommended that the exposed pad connect to the input voltage plane on the board. 12897-003 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 vout regulated output voltage. bypass the vout pin to the gnd pin with a 4.7 f or greater capacitor. 2 sense sense input. connect this pin to the vout pin. 3 va low noise reference voltage. connect a 1 f capacitor to gnd to reduce noise. do not connect a load to ground. 4 vafb output voltage reference feedback (adjust mode). connect a 1 nf to 1 f capacitor between the vafb pin and the va pin to reduce noise. start-up time is increased as a function of the capacitance. connect an external resistor divider between the va pin and the vafb pin to set the output voltage in adjust mode. 5 en enable. drive en at least +1.25 v above or ?1.3 v below ground to enable the regulator or drive en to ground to turn the regulator off. for automatic startup, connect en to vin. 6 gnd ground. 7 vreg regulated input supply to the ldo amplifier. bypass vre g to gnd with a 1 f or greater capacitor. do not connect a load to ground. 8 vin regulator input supply. bypass vin to gnd with a 4.7 f or greater capacitor. ep exposed pad. the exposed pad enhances the thermal perfor mance and is electrically connected to vin inside the package. it is recommended that the exposed pad connect to the input voltage plane on the board.
data sheet adp7183 rev. 0 | page 7 of 19 typical performance characteristics v in = ?3.8 v, v out = ?3.3 v, i out = ?10 ma, c in = c out = 4.7 f, c afb = 10 nf, c a = c reg = 1 f, t a = 25c, unless otherwise noted. v out (v) junction temperature (c) ?60 ?40 ?20 0 20 40 60 80 100 120 140 no load i load = ?10ma i load = ?100ma i load = ?300ma 12897-204 ?1.216 ?1.211 ?1.206 ?1.201 ?1.196 ?1.191 ?1.186 figure 4. output voltage (v out ) vs. junction temperature, v out = ?1.2 v v out (v) i load (ma) ?1000 ?100 ?10 12897-205 ?1.216 ?1.211 ?1.206 ?1.201 ?1.196 ?1.191 ?1.186 figure 5. output voltage (v out ) vs. load current (i load ), v out = ?1.2 v v out (v) v in (v) ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 no load i load = ?10ma i load = ?100ma i load = ?300ma 12897-206 ?1.246 ?1.236 ?1.226 ?1.216 ?1.206 ?1.196 ?1.186 figure 6. output voltage (v out ) vs. input voltage (v in ), v out = ?1.2 v ground current (ma) junction temperature (c) ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?15 ?40 10356085110135 no load i load =?10ma i load =?100ma i load =?300ma 12897-017 figure 7. ground current vs. junction temperature (t j ), v out = ?1.2 v i load (ma) ?300 ?200 ?100 0 ground current (ma) ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 12897-018 figure 8. ground current vs. load current (i load ), v out = ?1.2 v ground current (ma) v in (v) ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 no load i load = ?10ma i load = ?100ma i load = ?300ma 12897-019 figure 9. ground current vs. input voltage (v in ), v out = ?1.2 v
adp7183 data sheet rev. 0 | page 8 of 19 shutdown current (a) junction temperature (c) ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?40 ?15 10 35 60 85 110 135 v in = ?2.0v v in = ?2.5v v in = ?3.0v v in = ?3.5v v in = ?4.0v v in = ?4.5v v in = ?5.0v v in = ?5.5v 12897-020 figure 10. shutdown current vs. junction temperature at various input voltages, v out = ?1.2 v ?2.555 ?2.535 ?2.515 ?2.495 ?2.475 ?2.455 ?2.435 v out (v) junction temperature (c) ?60 ?40 ?20 0 20 40 60 80 100 120 140 no load i load =?10ma i load = ?100ma i load = ?300ma 12897-211 figure 11. output voltage (v out ) vs. junction temperature (t j ), v out = ?2.5 v v out (v) i load (ma) ?1000 ?100 ?10 12897-212 ?2.555 ?2.535 ?2.515 ?2.495 ?2.475 ?2.455 figure 12. output voltage (v out ) vs. load current (i load ), v out = ?2.5 v v out (v) v in (v) ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 no load i load =?10ma i load = ?100ma i load = ?300ma 12897-213 ?2.575 ?2.555 ?2.535 ?2.515 ?2.495 ?2.475 ?2.455 ?2.435 figure 13. output voltage (v out ) vs. input voltage (v in ), v out = ?2.5 v i load (ma) ?3.5 ?4.0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?300 ?200 ?100 ?250 ?150 ?50 0 ground current (ma) 12897-124 figure 14. ground current vs. load current (i load ), v out = ?2.5 v v in (v) ?3.5 ?4.0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?5.5 ?4.5 ?3.5 ?5.0?4.0?3.0 ground current (ma) 12897-125 i load =?10ma i load = ?100ma i load = ?200ma i load = ?300ma figure 15. ground current vs. input voltage (v in ), v out = ?2.5 v
data sheet adp7183 rev. 0 | page 9 of 19 dropout voltage (mv) i load (ma) ?1000 ?100 ?10 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 12897-029 figure 16. dropout voltage vs. load current (i load ), v out = ?2.5 v v out (v) v in (v) ?2.52 ?2.50 ?2.48 ?2.46 ?2.44 ?2.42 ? 2.36 ?2.38 ?2.40 ?3.1 ?3.0?2.9?2.8?2.7?2.6?2.5?2.4 no load i load =?10ma i load = ?100ma i load = ?300ma 12897-030 figure 17. output voltage (v out ) vs. input voltage (v in ) in dropout at various loads, v out = ?2.5 v v out (v) junction temperature (c) ?60 ?40 ?20 0 20 40 60 80 100 120 140 no load i load =?10ma i load = ?100ma i load = ?300ma 12897-218 ?3.359 ?3.339 ?3.319 ?3.299 ?3.279 ?3.259 ?3.239 figure 18. output voltage (v out ) vs. junction temperature (t j ), v out = ?3.3 v v out (v) i load (ma) ?1000 ?100 ?10 12897-219 ?3.369 ?3.349 ?3.329 ?3.309 ?3.289 ?3.269 ?3.249 figure 19. output voltage (v out ) vs. load current (i load ), v out = ?3.3 v v out (v) v in (v) no load i load =?10ma i load = ?100ma i load = ?300ma 12897-220 ?3.38 ?3.36 ?3.34 ?3.32 ?3.30 ?3.28 ?3.26 ?5.5 ?5.3 ?5.1 ?4.9 ?4.7 ?4.5 ?4.3 ?4.1 ?3.9 figure 20. output voltage (v out ) vs. input voltage (v in ), v out = ?3.3 v ground current (ma) junction temperature (c) ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?15 ?40 10 35 60 85 110 135 no load i load =?10ma i load = ?100ma i load = ?300ma 12897-007 figure 21. ground current vs. junction temperature (t j ), v out = ?3.3 v
adp7183 data sheet rev. 0 | page 10 of 19 i load (ma) ?3.5 ?4.0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?300 ?200 ?100 0 ground current (ma) 12897-008 figure 22. ground current vs. load current (i load ), v out = ?3.3 v ground current (ma) v in (v) ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?5.5 ?5.3 ?5.1 ?4.9 ?4.7 ?4.5 ?4.3 ?4.1 ?3.9 i load =no load i load = ?10ma i load = ?100ma i load = ?300ma 12897-009 figure 23. ground current vs. input voltage (v in ), v out = ?3.3 v shutdown current (a) junction temperature (c) ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 v in = ?3.8v v in = ?4.0v v in = ?4.5v v in = ?5.0v v in = ?5.5v ?40 ?20 0 20 40 60 80 100 120 140 12897-010 figure 24. shutdown current vs. junction temperature (t j ) at various input voltages, v out = ?3.3 v 12897-011 dropout voltage (mv) i load (ma) ?1000 ?100 ?10 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 figure 25. dropout voltage vs. load current (i load ), v out = ?3.3 v v out (v) v in (v) ?3.31 ? 3.21 ?3.22 ?3.23 ?3.24 ?3.25 ?3.26 ?3.27 ?3.28 ?3.29 ?3.30 ?3.9?3.8?3.7?3.6?3.5?3.4?3.3?3.2 no load i load =?10ma i load = ?100ma i load = ?300ma 12897-012 figure 26. output voltage (v out ) vs. input voltage (v in ) in dropout at various loads, v out = ?3.3 v ground current (ma) v in (v) ?25 ?20 ?15 ?10 ?5 0 ?3.9 ?2.7 ?2.8 ?2.9?3.0?3.1?3.2?3.3?3.4 ?3.5?3.6?3.7 ?3.8 i load = ?10ma i load = ?100ma i load = ?300ma 12897-013 figure 27. ground current vs. input voltage (v in ) in dropout at various loads, v out = ?3.3 v
data sheet adp7183 rev. 0 | page 11 of 19 psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m i load = ?10ma i load = ?100ma i load = ?200ma i load = ?300ma 12897-032 figure 28. power supply rejection ratio (psrr) vs. frequency at various loads, v out = ?1.2 v, v in = ?2 v psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m i load = ?10ma i load = ?100ma i load = ?200ma i load = ?300ma 12897-033 figure 29. power supply rejection ratio (psrr) vs. frequency at various loads, v out = ?2.5 v, v in = ?3 v psrr (db) frequency (hz) 1 10 100 1k 10k 100k 1m 10m ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 i load = ?10ma i load = ?100ma i load = ?200ma i load = ?300ma 12897-034 figure 30. power supply rejection ratio (psrr) vs. frequency at various loads, v out = ?3.3 v, v in = ?3.8 v psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m v in = ?2.0v v in = ?2.1v v in = ?2.2v v in = ?2.3v v in = ?2.4v v in = ?2.5v 12897-035 figure 31. power supply rejection ratio (psrr) vs. frequency at various input voltages, v out = ?1.2 v, i load = ?300 ma psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m v in = ?3.0v v in = ?3.1v v in = ?3.2v v in = ?3.3v v in = ?3.4v v in = ?3.5v 12897-036 figure 32. power supply rejection ratio (psrr) vs. frequency at various input voltages, v out = ?2.5 v, i load = ?300 ma psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m v in = ?3.8v v in = ?3.9v v in = ?4.0v v in = ?4.1v v in = ?4.2v v in = ?4.3v 12897-037 figure 33. power supply rejection ratio (psrr) vs. frequency at various input voltages, v out = ?3.3 v, i load = ?300 ma
adp7183 data sheet rev. 0 | page 12 of 19 rms noise (v rms) load current (ma) ?1000 ?100 ?10 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 10hz to 100khz 100hz to 100khz 12897-038 figure 34. rms noise vs. load current (i load ) at various frequencies nsd (nv/ 12897-235 figure 35. noise spectral density (nsd) vs . frequency at various output voltages 12897-139 ch1 500mv ch2 2.0mv 5.0s/div 1ms 20gsps a ch2 40mv 1 2 v in v out figure 36. line transient response, 500 mv step, v out = ?1.2 v, i load = ?300 ma 12897-140 ch1 500mv ch2 2.0mv 5.0s/div 1ms 20gsps a ch2 40mv 1 2 v in v out figure 37. line transient response, 500 mv step, v out = ?3.3 v, i load = ?300 ma 12897-141 ch1 200ma ch2 2.00mv m10.00s a ch1 ?222ma 1 2 t 21.4s t i load v out figure 38. load transient response, v out = ?1.2 v, i load = ?10 ma to ?300 ma 12897-142 ch1 200ma ch2 2.00mv m10.00s a ch1 ?200ma 1 2 t 21.2s t i load v out figure 39. load transient response, v out = ?2.5 v, i load = ?10 ma to ?300 ma
data sheet adp7183 rev. 0 | page 13 of 19 theory of operation the adp7183 is a low quiescent current, ldo linear regulator that operates from ?2.0 v to ?5.5 v and can provide up to ?300 ma of output current. total integrated output noise is 4 v rms independent of the output voltage, making it ideal for high performance and noise sensitive applications. shutdown current consumption is ?7 a (maximum). the adp7183 is optimized for use with a 4.7 f ceramic capacitor for excellent transient performance. using advanced proprietary architecture, the adp7183 provides ultralow noise and high power supply rejection up to high frequencies of operation. figure 40 shows the fixed output voltage internal block diagram of the adp7183 , and figure 41 show the adjustable output voltage internal block diagram of the adp7183 . r1 r2 vafb overcurrent thermal protection reference ?0.5v reg gnd vreg en vin va sense vout g m en 12897-046 figure 40. fixed output voltage internal block diagram overcurrent thermal protection reference ?0.5v reg gnd vreg en vin g m en vafb va sense vout r1 r2 12897-047 figure 41. adjustable output voltage internal block diagram internally, the adp7183 consists of a regulator block, reference block, g m amplifier, feedback voltage divider, ldo regulator and a n channel mosfet pass transistor. the regulator block produces an internal voltage rail (v reg ) of ?1.8 v to serve as the supply voltage for the succeeding internal blocks. the g m amplifier produces a reference voltage (v a ) used as a reference to the ldo regulator. for fixed option models, the v a voltage is generated through the resistor divider ratio depending on the v out option. for adjustable models, the v a voltage generates externally through the r1 and r2 resistors that are connected across the va and vafb pins. because the reference voltage to the ldo regulator already adjusts according to the desired v out , the ldo regulator now connects in a buffer configuration for improved noise performance. if the load draws higher current, the ldo regulator pulls the gate of the nmos device higher towards gnd to allow more current to pass. if the load draws less current, the ldo regulator pulls the gate of the nmos device lower toward ?v in to restrict the amount of current passing through the device. adjustable mode operation the adjustable mode version of the adp7183 has an output that can be set to from ?0.5 v to ?4.5 v by an external voltage divider. to calculate the output voltage, use the following equation: v out = ?0.5 v(1 + r1 / r2 ) (1) figure 42 shows an example of an adjustable setting where r1 = 280 k and r2 = 49.9 k, setting the output voltage to ?3.3 v. r2 must be at least 10 k to maximize psrr performance. c in 4.7f v in = ?3.8v +1.25v 0v ?1.3v off on v out = ?3.3v c reg 1f vin vreg gnd en vout sense va vafb adp7183 c out 4.7f c a 1f r1 280k ? r2 49.9k ? c afb 10nf ep 12897-048 figure 42. setting the adjustable output voltage enable pin operation the adp7183 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is +1.25 v above or ?1.3 v below with respect to gnd, vout turns on and when en is at 0 v, vout turns off, as shown in figure 43. for automatic startup, connect en to vin. 12897-149 ch2 1.0v ?15mv ch3 1.0v 0mv 200ms/div 2ms 1msps a ch2 40mv 3 en v out figure 43. typical en pin operation
adp7183 data sheet rev. 0 | page 14 of 19 start-up time when the output is enabled, the adp7183 uses an internal soft start to limit the inrush current. the start-up time for a ?1.2 v output is approximately 12 ms from the time the en active threshold is crossed to the time when the output reaches 90% of its final value (see figure 44). as shown in figure 44 and figure 45, the start-up time is dependent upon the output voltage option and the value of the c afb capacitor. v out , en (v) time (ms) en v out = ?4.5v v out = ?3.3v v out = ?2.5v v out = ?1.2v ?6 ?5 ?4 ?3 ?2 ?1 0 1 12897-244 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 figure 44. start-up time at various output voltages, c afb = 10 nf, c a = 1 f the total start-up time depends mostly on the c a and c afb values expressed by the 1 and 2 equations (see equation 1 and equation 2). during startup, an internal circuit, g m_start , turns on and helps charge c a up to 90% of the final value. estimate the first time constant, 1 , due to c a by 1 c a (( r1 + r2 ) // z out ) (2) during this time, keep z out low to approximately 1 k to allow quick start-up times, keeping 1 in the order of 1 ms. v out (v) time (ms) 12897-245 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 10 30 50 70 90 110 130 150 170 190 210 230 en c afb = 1nf c afb = 10nf c afb = 100nf c afb = 1f figure 45. start-up time at various c afb capacitor values, c a = 1 f a second time constant, 2 , is dependent mainly on c afb . figure 45 shows how the c afb value affects the start-up time. estimate 2 by 2 c afb r1 (3) the r1 value scales vs. the v out option. table 6 shows the r1 value depending on the fixed output voltage option, whereas r2 is constant at 500 k. for example, at a fixed v out = ?3.3 v, r1 is equal to 2.8 m. to keep 2 at a minimum, it is recommended that c afb be in the approximately nanofarad range. a typical setup for the adp7183 is c afb = 10 nf; therefore, 2 = 28 ms. the total time constant, total , is the sum of 1 and 2 . at 2.2 total , va is equal to ~90% of the final value. therefore, for a fixed v out = ?3.3 v, the output voltage is ~90% of the final value after 63.8 ms. table 6. r1 and r2 values for the fixed output options output voltage (v) r1 () r2 (k) ?1.2 700 k 500 ?2.5 2 m 500 ?3.3 2.8 m 500 ?4.5 4 m 500 note that 1 and 2 are estimates only and do not take into account that g m and z out dynamically change. it is an accurate estimate of ~90% of the start-up time for the c afb < 10 nf recommended setup, where ~100% of the settling time can easily be achieved. note that for setups with c afb >> 10 nf, the equation may not hold true anymore. however, it is still a convenient estimate on the amount of time needed to ac hieve ~100% of the settling time.
data sheet adp7183 rev. 0 | page 15 of 19 applications information adisimpower design tool the adisimpower ? design tool set supports the adp7183 . adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count, taking into consideration the operating conditions and limitations of the ic and all external components. for more information about, and to obtain adisimpower design tools, visit www.analog.com/adisimpower . capacitor selection output capacitor the adp7183 operates with small, space-saving ceramic capacitors; however, it functions with general-purpose capacitors as long as care is taken with regard to the esr value. the esr of the output capacitor affects the stability of the ldo regulator control loop. a minimum of 4.7 f capacitance with an esr of 0.05 or less is recommended to ensure the stability of the adp7183 . output capacitance affects the transient response to changes in load currents. using a larger value for the output capacitance improves the transient response of the adp7183 to large changes in load current. figure 46 shows the transient response for an output capacitance value of 4.7 f. 12897-300 ch1 200ma ch2 2.00mv m10.00s a ch1 ?222ma 1 2 t 21.4s t i load v out figure 46. output transient response, c out = 4.7 f, v out = ?1.2 v input bypass capacitor connecting a 4.7 f or greater capacitor from vin to gnd reduces the circuit sensitivity to the pcb layout, especially when long input traces or high source impedance are encountered. when more than 4.7 f of output capacitance is required, increase the input capacitance to match it. c a and c afb capacitors the ultralow output noise of the adp7183 is achieved by keeping the ldo error amplifier in unity gain and setting the reference voltage equal to the output voltage. in this architecture, the resistor driven by the g m amplifier adjusts the reference voltage to the selected output voltage. to ensure the g m amplifier stability, the c a capacitor is needed to generate the dominant pole and to keep the g m amplifier stable across all conditions. c a also serves as a dampening capacitor to the inputs of the ldo error amplifier for improved psrr. however, the ldo output noise scales by the g m amplifier amount of gain as a function of the output voltage. to minimize the output voltage noise contributed by the g m amplifier, the c afb capacitor must be connected between the va and vafb pins to keep the ac gain of the g m amplifier in unity. reference g m va vafb gnd c afb c a r2 r1 12897-100 figure 47. c a and c afb connection to g m amplifier input and output capacitor properties any good quality ceramic capacitors can be used with the adp7183 if they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r and x7r dielectrics with a voltage rating from 6.3 v to 10 v are recommended. due to their poor temperature and dc bias characteristics, y5v and z5u dielectrics are not recommended.
adp7183 data sheet rev. 0 | page 16 of 19 figure 48 shows the capacitance change vs. the bias voltage characteristics of a 0805 case, 4.7 f, 10 v, x5r capacitor. the capacitor size and voltage rating strongly influences the voltage stability of a capacitor. in general, a capacitor in a larger package or with a higher voltage rating exhibits improved stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c temperature range and is not a function of package size or voltage rating. 0 024681012 change in capacitance (f) dc bias voltage (v dc) 5.64 4.70 1.88 2.82 3.76 0.94 12897-053 figure 48. change in capacitance vs. dc bias voltage use equation 4 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c out (1 ? tempco ) (1 ? tol) (4) where: c eff is the effective capacitance at the operating voltage. c out is the output capacitor. tempco is the worst case capacitor temperature coefficient. tol is the worst case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out = 4.7 f at 1.0 v. substituting these values in equation 4 yields c eff = 4.7 f (1 ? 0.15) (1 ? 0.1) = 3.6 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo regulator over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp7183 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. undervoltage lockout (uvlo) the uvlo circuitry protects the system from power supply brownouts. if the input voltage on vin is more positive than the minimum ?1.58 v uvlo falling threshold, the ldo output shuts down. the ldo enables again when the voltage to vin is more negative than the maximum ?1.77 v uvlo rising threshold. a typical hysteresis of 90 mv within the uvlo circuitry prevents the device from oscillating due to the noise from vin. 0.05 0 ?0.55 ?1.80 ?1.60 v out (v) v in (v) ?1.78 ?1.76 ?1.74 ?1.72 ?1.70 ?1.68 ?1.66 ?1.64 ?1.62 ?0.50 ?0.45 ?0.40 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 12897-054 figure 49. typical uvlo behavior, v out = ?0.5 v current-limit and thermal overload protection the adp7183 is protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. the adp7183 is designed to reach the current limit when the output load reaches ?600 ma (typical). when the output load exceeds ?600 ma, the output voltage reduces to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a threshold of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 150c, the output turns off, reducing the output current to zero. when the junction temperature drops below 135c (typical), the output turns on again, and the output current is restored to its nominal value. consider the case where a hard short from vout to gnd occurs. at first, the adp7183 reaches the current limit so that only ?600 ma is conducted into the short. if self heating of the junction becomes great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to 0 ma. as the junction temperature cools and drops below 135c, the output turns on and conducts ?600 ma into the short circuit, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between ?600 ma and 0 ma that continues as long as the short remains at the output. current-limit and thermal overload protections protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125c.
data sheet adp7183 rev. 0 | page 17 of 19 thermal considerations in applications with a low input-to-output voltage differential, the adp7183 does not dissipate much heat. however, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough to cause the junction temperature of the die to exceed the maximum junction temperature of 125c. when the junction temperature exceeds 150c, the converter enters thermal shutdown. the converter recovers only after the junction temperature decreases below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in equation 5. to guarantee reliable operation, the junction temperature of the adp7183 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used, and the amount of copper used to solder the package vin pins to the pcb. table 7 shows the typical ja values for the 8-lead lfcsp package for various pcb copper sizes. table 7. typical ja values for the 8-lead lfcsp copper size (mm 2 ) ja (c/w) 25 146.6 100 105.4 500 75.38 1000 65.16 6400 53.5 calculate the junction temperatures of the adp7183 by t j = t a + ( p d ja ) (5) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = (( v in ? v out ) i load ) + ( v in i gnd ) (6) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to t j = t a + ((( v in ? v out ) i load ) ja ) (7) as shown in equation 7, for a given ambient temperature, input-to-output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure that the junction temperature does not rise above 125c. figure 50 to figure 52 show the junction temperature calculations for the different ambient temperatures, power dissipation, and areas of the pcb copper. 140 0 20 40 60 100 80 120 01.6 junction temperature (c) total power dissipation (w) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t j max 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 12897-055 figure 50. junction temperature vs. total power dissipation, t a = 25c 140 0 20 40 60 100 80 120 01.6 junction temperature (c) total power dissipation (w) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t j max 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 12897-056 figure 51. junction temperature vs. total power dissipation, t a = 50c 140 0 20 40 60 100 80 120 1.6 junction temperature (c) total power dissipation (w) t j max 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 0.2 0 0.4 0.6 0.8 1.0 1.2 1.4 12897-057 figure 52. junction temperature vs. total power dissipation, t a = 85c
adp7183 data sheet rev. 0 | page 18 of 19 pcb layout considerations place the input capacitor (c in ) as close as possible to the vin and gnd pins. place the output capacitor (c out ) as close as possible to the vout and gnd pins. place bypass capacitors (c a and c reg ) close to the respective pins (va and vreg) and gnd. use of 0805 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. connect the exposed pad to vin. 12897-059 figure 53. evaluation board 12897-060 figure 54. typical board layout, top side 12897-061 figure 55. typical board layout, bottom side
data sheet adp7183 rev. 0 | page 19 of 19 outline dimensions 1.60 1.50 1.40 0.30 0.25 0.20 top view side view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area 0.60 0.55 0.50 1.10 1.00 0.90 0.152 ref 0.05 max 0.02 nom 0.50 bsc exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-24-2016-a pkg-004752 2.10 2.00 sq 1.90 seating plane p i n 1 i n d i c a t o r a r e a o p t i o n s ( s e e d e t a i l a ) detail a (jedec 95) figure 56. 8-lead lead frame chip scale package [lfcsp] 2 mm 2 mm body and 0.55 mm package height (cp-8-27) dimensions shown in millimeters ordering guide model 1 temperature range output voltage (v) 2 package description package option branding adp7183acpzn0.5-r7 ?40c to +125c ?0.5 8-lead lfcsp cp-8-27 ls9 adp7183acpzn1.0-r7 ?40c to +125c ?1.0 8-lead lfcsp cp-8-27 lsa adp7183acpzn1.2-r7 ?40c to +125c ?1.2 8-lead lfcsp cp-8-27 lsb adp7183acpzn1.5-r7 ?40c to +125c ?1.5 8-lead lfcsp cp-8-27 lsc adp7183acpzn1.8-r7 ?40c to +125c ?1.8 8-lead lfcsp cp-8-27 lsd adp7183acpzn2.0-r7 ?40c to +125c ?2.0 8-lead lfcsp cp-8-27 lss adp7183acpzn2.5-r7 ?40c to +125c ?2.5 8-lead lfcsp cp-8-27 lse adp7183acpzn3.0-r7 ?40c to +125c ?3.0 8-lead lfcsp cp-8-27 lsf adp7183acpzn3.3-r7 ?40c to +125c ?3.3 8-lead lfcsp cp-8-27 ltm adp7183acpzn-r7 ?40c to +125c adjustable 8-lead lfcsp cp-8-27 ltn adp7183-3.3-evalz ?3.3 evaluation board for the fixed voltage option adp7183-adj-evalz ?2.5 evaluation board for the adjustable voltage option 1 z = rohs compliant part. 2 for additional voltage options, contact a local analog devices inc., sales or distribution representative. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12897-0-10/16(0)

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